New theoretical results on quadratic placement

Current tools for VLSI placement are based either on quadratic placement, or on min-cut heuristics, or on simulated annealing. For the most complex chips with millions of movable objects, algorithms based on quadratic placement seem to yield the best results within reasonable time. In this paper we prove several new theoretical results on quadratic placement. We point out connections to random walks and electrical networks. Moreover, we argue that quadratic placement has, in contrast to the other approaches, some well-defined stability properties. Finally, we consider the question how to choose the weights of the clique edges representing a multiterminal net optimally. 1 Global Placement Approaches VLSI placement is a very hard problem in theory and practice. The strongest theoretical results, due to Even, Guha and Schieber [14], Even, Naor, Rao and Schieber [15], Vempala [32], and Brenner [5], give polylogarithmic approximations for variants of the placement problem. Even the simplest one-dimensional variant, the Optimum Linear Arrangement Problem, is NP-hard [21], but has at least an O(log |V (G)|)-factor approximation algorithm [29]. As the running times and approximation guarantees of these algorithms are quite weak, they are of very limited use in practice. Practical algorithms must be very fast, and one has to accept that no approximation guarantee (no matter in which respect) can be given. In fact, there are no useful techniques for proving lower bounds on the minimum netlength of a placement instance. On the other hand, strong inapproximability results are also missing for all natural variants of the placement problem. Three basic approaches to global placement are used in practice. One of them is local search, most notably simulated annealing (see [36, 30, 26]). Local search techniques have the advantage that almost arbitrary constraints and objective functions, as long as they can be evaluated fast enough, can be incorporated. One can also make simulated annealing converge to the global optimum in finite time, but the resulting time bounds are not much stronger than for complete enumeration of all feasible placements. In practice, simulated annealing (with well-tuned parameters) and other local search techniques can yield good results, but only at the cost of an immense running time. Nevertheless they are still used in practice, in particular for small instances. Local search techniques can be particularly useful for improving placements locally that have been obtained in an other way [16]. The second approach to placement is recursive partitioning. Very roughly, the chip area is divided by horizontal and/or vertical lines into two or four rectangular regions, and 1 the circuits are assigned to these such that none of the regions contains more than would fit into it. The most popular objective is minimizing the number of nets whose pins belong to circuits that are not all assigned to the same region. If a net contains pins outside the region which is currently partitioned, then these are projected to the closest of the subregions into which we are about to partition (this technique is sometimes called terminal propagation). The motivation of this min-cut approach is clear: summing up these objective function values while recursively partitioning the chip area to a unit grid yields precisely the bounding box netlength. See [7] for an early reference. However, the min-cut approach has serious disadvantages: Firstly, minimizing the first cut may lead to very poor cuts in the subsequent partitioning steps. Secondly, minimizing the number of cut edges is a very hard problem: it includes the Minimum Bisection Problem, which asks for partitioning the vertex set of a given graph G into V (G) = V1 . ∪ V2 such that |V1| = |V2| and |{e = {v, v′} ∈ E(G) : v ∈ V1, v′ ∈ V2}| is minimum. This problem is NP-hard [21] and cannot be solved within an additive term of |V (G)|2− for any > 0, unless P = NP [8]. This remains true if we allow partitions into two sets of approximately equal cardinality. However, none of these results excludes the possibility of an approximation scheme. On the other hand, the best known approximation algorithm, due to Feige and Krauthgamer [17], has a performance ratio of O(log |V (G)|). In practice one uses heuristics, mostly based on Fiduccia’s and Mattheyses’ [18] variant of the exchange heuristic proposed by Kernighan and Lin [24], combined with multilevel clustering. See [3] for a comprehensive survey. As will be shown in Section 4, a further disadvantage of both local search and min-cut approaches is their inherent instability. The third approach, sometimes called analytical placement, first ignores the constraint that circuits must not overlap and just minimizes some netlength estimation. This makes the placement problem much easier. For example, minimizing the (weighted) bounding box netlength is equivalent to the dual of an uncapacitated Minimum Cost Flow Problem. The fastest algorithms [27, 35] solve this in O(n log n(m + n log n)) time, where n := |C|+ |N |, m := |P |, and C, N and P denote the set of circuits, nets and pins, respectively. This is applicable for medium-complex chips, but current minimum cost flow algorithms seem to be too slow for instances with millions of circuits. This is one motivation for minimizing a quadratic objective function, e.g. the weighted sum of the squared Euclidean distances of connected pairs of pins. One can consider the two dimensions separately and obtains two quadratic programs of the following type: min ∑